divclk1hz dc(reset,clk50,clk1); always@(posedge clk1,posedge key,posedge flagclk,posedge up,posedge down) begin if(key) begin hour=0; minutes=0; seconds=0; out5=hour/10; out4=hour%10; out3=minutes/10; out2=minutes%10; out1=seconds/10; out0=seconds%10; end elseif(flagclk) begin flag=(flag+1)%4; end elseif(up) begin if(flag==1) begin if(hour<23) hour=hour+1; else hour=0; end if(flag==2) begin if(minutes<59) minutes=minutes+1; else minutes=0; end if(flag==3) begin if(seconds<59) seconds=seconds+1; else seconds=0; end out5=hour/10; out4=hour%10; out3=minutes/10; out2=minutes%10; out1=seconds/10; out0=seconds%10; end elseif(down) begin if(flag==1) begin if(hour>0) hour=hour-1; else hour=23; end if(flag==2) begin if(minutes>0) minutes=minutes-1; else minutes=59; end if(flag==3) begin if(seconds>0) seconds=seconds-1; else seconds=59; end out5=hour/10; out4=hour%10; out3=minutes/10; out2=minutes%10; out1=seconds/10; out0=seconds%10; end
else begin if(seconds<59) seconds=seconds+1; else begin if(seconds==59) begin seconds=0; if(minutes<59) minutes=minutes+1; else begin if(minutes==59) begin minutes=0; if(hour<23) hour=hour+1; else begin if(hour==23) hour=0; end end end end end
out5=hour/10; out4=hour%10; out3=minutes/10; out2=minutes%10; out1=seconds/10; out0=seconds%10; end end
module divclk1hz(reset,clk50,clk1); input clk50,reset; outputreg clk1=1; integer i=0; always@(posedge clk50) begin if(!reset) begin i=1; end else begin if(i==250) begin i=1; clk1=~clk1; end else i=i+1; end end endmodule